cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07721 rev. *b revised june 07, 2007 cy62168ev30 mobl ? 16-mbit (2m x 8) static ram features ? very high speed: 45 ns ? wide voltage range: 2.20v ? 3.60v ? ultra low standby power ? typical standby current: 1.5 a ? maximum standby current: 12 a ? ultra low active power ? typical active current: 2.2 ma @ f = 1 mhz ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power down when deselected ? cmos for optimum speed/power ? offered in pb-free 48-ball fbga package. for pb-free 48-pin tsop i package, refer to cy62167ev30 data sheet. functional description [1] the cy62168ev30 is a high performance cmos static ram organized as 2m words by 8 bits. this device features advanced circuit design to provide an ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (chip enable 1 (ce 1 ) high or chip enable 2 (ce 2 ) low). the input and output pins (io 0 through io 7 ) are placed in a high impedance state when: the device is deselected (chip enable 1 (ce 1 ) high or chip enable 2 (ce 2 ) low), outputs are disabled (oe high), or a write operat ion is in progress (chip enable 1 (ce 1 ) low and chip enable 2 (ce 2 ) high and we low). write to the device by taking chip enable 1 (ce 1 ) low and chip enable 2 (ce 2 ) high and the write enable (we) input low. data on the eight io pins (io 0 through io 7 ) is then written into the location specified on the address pins (a 0 through a 20 ). read from the device by taking chip enable 1 (ce 1 ) and output enable (oe ) low and chip enable 2 (ce 2 ) high while forcing write enable (we ) high. under these condi- tions, the contents of the memo ry location specified by the address pins will appear on the io pins. the eight input and output pins (io 0 through io 7 ) are placed in a high impedance state when the device is deselected (ce 1 low and ce 2 high), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low). see the ?truth table? on page 8 for a complete description of read and write modes. logic block diagram a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 2m x 8 array data in drivers a 10 a 11 a 17 ce 1 ce 2 a 12 a 18 a 19 a 20 note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . [+] feedback [+] feedback
document #: 001-07721 rev. *b page 2 of 10 cy62168ev30 mobl ? pin configuration [2] 48-ball fbga top view product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62168ev30ll 2.2 3.0 3.6 45 2.2 4.0 25 30 1.5 12 we v cc a 0 ce 1 oe v ss ce 2 nc v cc 3 2 6 5 4 1 d e b a c f g h v ss a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 16 a 14 a 15 a 12 a 13 a 9 a 10 a 8 a 18 a 11 a 19 io 0 io 1 io 2 io 3 a 20 io 4 io 5 io 6 io 7 nc nc nc nc nc nc nc nc nc nc notes 2. nc pins are not connected on the die. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25c. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 3 of 10 cy62168ev30 mobl ? maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ....................................... ?0.3v to v cc (max) + 0.3v dc voltage applied to outputs in high-z state [4, 5] ....................... ?0.3v to v cc (max) + 0.3v dc input voltage [4, 5] .................... ?0.3v to v cc (max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ...... > 2001v (mil-std-883, method 3015) latch up current..................................................... > 200 ma operating range range ambient temperature (t a ) [6] v cc [7] industrial ?40c to +85c 2.2v ? 3.6v dc electrical characteristics over the operating range parameter description test conditions cy62168ev30-45 unit min typ [3] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ? 0.1 ma 2.0 v 2.7 < v cc < 3.6 i oh = ? 1.0 ma 2.4 v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma 0.4 v 2.7 < v cc < 3.6 i oh = 2.1 ma 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 v cc + 0.3 v 2.7 < v cc < 3.6 2.2 v cc + 0.3 v il input low voltage 2.2 < v cc < 2.7 ?0.3 0.6 v 2.7 < v cc < 3.6 ?0.3 0.8 i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v, i out = 0 ma, cmos level 25 30 ma f = 1 mhz 2.2 4.0 i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f= 0 (oe , we ) 1.5 12 a i sb2 [8] automatic ce power down current? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v 1.5 12 a capacitance [9] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc (typ) 8pf c out output capacitance 10 pf notes 4. v il (min) = ?0.2v for pulse durations less than 20 ns. 5. v ih (max) = v cc + 0.75v for pulse durations less than 20 ns. 6. t a is the ?instant-on? case temperature. 7. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 100 s wait time after v cc stabilization. 8. only chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. 9. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 4 of 10 cy62168ev30 mobl ? thermal resistance [9] parameter description test conditions bga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 c/w jc thermal resistance (junction to case) 16 c/w ac test loads and waveforms parameters 2.5v (2.2v to 2.7v) 3.0v (2.7v to 3.6v) unit r1 16600 1103 ? r2 15400 1554 ? r th 8000 645 ? v th 1.2 1.75 v data retention characteristics over the operating range parameter description conditions min typ [3] max unit v dr v cc for data retention 1.5 3.6 v i ccdr [8] data retention current v cc = 1.5v ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v 10 a t cdr [9] chip deselect to data retention time 0ns t r [10] operation recovery time t rc ns data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce 1 v cc ce 2 or note 10. full device ac operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) > 100 s. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 5 of 10 cy62168ev30 mobl ? switching characteristics over the operating range [11] parameter description 45 ns unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low z [12] 5ns t hzoe oe high to high z [12, 13] 18 ns t lzce ce 1 low and ce 2 high to low z [12] 10 ns t hzce ce 1 high or ce 2 low to high z [12, 13] 18 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high or ce 2 low to power down 45 ns write cycle [14] t wc write cycle time 45 ns t sce ce 1 low and ce 2 high to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high z [12, 13] 18 ns t lzwe we high to low z [12] 10 ns notes 11. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1v/ns), ti ming reference levels of v cc (typ)/2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh as shown in ?ac test loads and waveforms? on page 4 . 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 13. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 14. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the s ignal that terminates the write. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 6 of 10 cy62168ev30 mobl ? switching waveforms figure 1 shows address transition controlled read cycle waveforms. [15, 16] figure 1. read cycle no. 1 figure 2 shows oe controlled read cycle waveforms. [16, 17] figure 2. read cycle no. 2 previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce 1 address ce 2 data out v cc supply current high i cc i sb impedance notes 15. the device is continuously selected. oe , ce 1 = v il , and ce 2 = v ih . 16. we is high for read cycle. 17. address valid before or similar to ce 1 transition low and ce 2 transition high. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 7 of 10 cy62168ev30 mobl ? figure 3 shows we controlled write cycle waveforms. [14, 18, 19] figure 3. write cycle no. 1 figure 4 shows ce 1 or ce 2 controlled write cycle waveforms. [14, 18, 19] figure 4. write cycle no. 2 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data note 20 ce 1 address ce 2 we data io oe t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t sa note 20 ce 1 address ce 2 we data io oe notes 18. data io is high impedance if oe = v ih . 19. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 20. during this period the ios are in output state. do not apply input signals. [+] feedback [+] feedback
document #: 001-07721 rev. *b page 8 of 10 cy62168ev30 mobl ? figure 5 shows we controlled, oe low write cycle waveforms. [19] figure 5. write cycle no. 3 truth table ce 1 ce 2 we oe inputs/outputs mode power h x x x high z deselect/power down standby (i sb ) x l x x high z deselect/power down standby (i sb ) l h h l data out (io 0 -io 7 )read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in (io 0 -io 7 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62168ev30ll-45bvxi 51-85150 48-ball fine pitch bga (pb-free) industrial contact your local cypress sales repres entative for availability of these parts. switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe note 20 ce 1 address ce 2 we data io [+] feedback [+] feedback
cy62168ev30 mobl ? document #: 001-07721 rev. *b page 9 of 10 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-e xclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the so le purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, tran slation, compilation, or representation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or im plied, with regard to this mate rial, including, but not limited to, the implied war- ranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further not ice to the materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. package diagrams figure 6. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d [+] feedback [+] feedback
document #: 001-07721 rev. *b page 10 of 10 cy62168ev30 mobl ? document history page document title: cy62168ev30 mobl ? 16-mbit (2m x 8) static ram document number: 001-07721 rev. ecn no. issue date orig. of change description of change ** 457686 see ecn nxr new data sheet *a 464509 see ecn nxr removed tsop i package; added reference to cy62167ev30 tsop i package which can be used as a 2m x 8 sram changed the i sb2(typ) value from 1.3 a to 1.5 a changed the i cc(typ) value from 2 ma to 2.2 ma for f=1mhz test condition changed the i cc(typ) value from 15 ma to 22 ma and i cc(max) value from 40 ma to 25 ma for f=1mhz test condition changed the i ccdr(max) value from 8.5 a to 8 a *b 1138883 see ecn vkn converted from preliminary to final changed i cc(max) spec from 2.8 ma to 4.0 ma for f=1mhz changed i cc(typ) spec from 22 ma to 25 ma for f=f max changed i cc(max) spec from 25 ma to 30 ma for f=f max added footnote# 8 related to i sb2 and i ccdr changed i sb1 and i sb2 spec from 8.5 a to 12 a changed i ccdr spec from 8 a to 10 a [+] feedback [+] feedback
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